Chapter 41 gmac ethernet Interface


T-chip GRF Register Summary


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T-chip
GRF Register Summary





GRF Register

Register Description

GRF_SOC_CON1[8:6]



PHY interface select 3'b001: RGMII
3'b100: RMII
All others: Reserved

GRF_SOC_CON1[9]



GMAC transmit flow control
When set high, instructs the GMAC to transmit PAUSE Control frames in Full-duplex mode. In Half-duplex mode, the GMAC enables the Back-pressure function
until this signal is made low again

GRF_SOC_CON1[10]



gmac_speed
1'b1: 100-Mbps 1'b0: 10-Mbps

GRF_SOC_CON1[11]



RMII clock selection 1'b1: 25MHz
1'b0: 2.5MHz

GRF_SOC_CON1[13:12]



RGMII clock selection 2'b00: 125MHz
2'b11: 25MHz
2'b10: 2.5MHz

GRF_SOC_CON1[14]



RMII mode selection 1'b1: RMII mode
1’b0: Reserved

GRF_SOC_CON3[6:0]

RGMII TX clock delayline value

GRF_SOC_CON3[13:7]

RGMII RX clock delayline value

GRF_SOC_CON3[14]

RGMII TX clock delayline enable


Only

T-chip






1'b1: enable 1'b0: disable

GRF_SOC_CON3[15]



RGMII RX clock delayline enable 1'b1: enable
1'b0: disable





FuZhou Rockchip Electronics Co.,Ltd.




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