Bit
|
Attr
|
Reset Value
|
Description
|
13
|
RW
|
0x0
|
FBE
Fatal Bus Error Enable
When this bit is set with Abnormal Interrupt Summary Enable (BIT 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset,
Fatal Bus Error Enable Interrupt is disabled.
|
12:11
|
RO
|
0x0
|
reserved
|
10
|
RW
|
0x0
|
ETE
Early Transmit Interrupt Enable When this bit is set with an Abnormal
Interrupt Summary Enable (BIT 15), Early Transmit Interrupt is enabled. When this bit is
reset, Early Transmit Interrupt is disabled.
|
9
|
RW
|
0x0
|
RWE
Receive Watchdog Timeout Enable
When this bit is set with Abnormal Interrupt Summary Enable (BIT 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, Receive
Watchdog Timeout Interrupt is disabled.
|
8
|
RW
|
0x0
|
RSE
Receive Stopped Enable
When this bit is set with Abnormal Interrupt Summary Enable (BIT 15), Receive Stopped Interrupt is enabled. When this bit is reset, Receive Stopped Interrupt is disabled.
|
7
|
RW
|
0x0
|
RUE
Receive Buffer Unavailable Enable
When this bit is set with Abnormal Interrupt Summary Enable (BIT 15), Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled
|
6
|
RW
|
0x0
|
RIE
Receive Interrupt Enable
When this bit is set with Normal Interrupt Summary Enable (BIT 16), Receive Interrupt is enabled. When this bit is reset, Receive Interrupt is disabled.
|
5
|
RW
|
0x0
|
UNE
Underflow Interrupt Enable
When this bit is set with Abnormal Interrupt Summary Enable (BIT 15), Transmit Underflow Interrupt is enabled. When this bit is reset, Underflow Interrupt is disabled.
|
