Chapter 41 gmac ethernet Interface


Detail Register Description


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Detail Register Description




GMAC_MAC_CONF


Address: Operational Base + offset (0x0000) MAC Configuration Register

Bit

Attr

Reset Value

Description

31:25

RO

0x0

reserved

24


RW


0x0


TC
Transmit Configuration in RGMII/SGMII/SMII When set, this bit enables the transmission of duplex mode, link speed, and link up/down information to the PHY in the RGMII ports.
When this bit is reset, no such information is
driven to the PHY.


Only

T-chip



Bit

Attr

Reset Value

Description

23

RW

0x0

WD
Watchdog Disable
When this bit is set, the GMAC disables the watchdog timer on the receiver, and can receive frames of up to 16,384 bytes.
When this bit is reset, the GMAC allows no more than 2,048 bytes (10,240 if JE is set high) of the frame being received and cuts off
any bytes received after that.

22

RW

0x0

JD
Jabber Disable
When this bit is set, the GMAC disables the jabber timer on the transmitter, and can transfer frames of up to 16,384 bytes.
When this bit is reset, the GMAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set
high) during transmission.

21

RW

0x0

BE
Frame Burst Enable
When this bit is set, the GMAC allows frame bursting during transmission in GMII
Half-Duplex mode.

20

RO

0x0

reserved

19:17

RW

0x0

IFG
Inter-Frame Gap
These bits control the minimum IFG between frames during transmission.
3'b000: 96 bit times 3'b001: 88 bit times 3'b010: 80 bit times
...
3'b111: 40 bit times

16


RW


0x0


DCRS
Disable Carrier Sense During Transmission When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in Half-Duplex mode. This request results in no errors generated due to Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors due to Carrier Sense and will even abort the
transmissions.


Only

T-chip




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