High speed, low driving voltage vertical cavity germanium-silicon modulators for optical

3.4.2 Direct Buffer Growth 
Since the QCSE is based on absorption, a moderate level of threading dislocations is 
acceptable. On the other hand, a thin buffer is preferred for optical device design in 
practice. Since temperature affects growth rate dramatically in the regime this work 
focus on, growth should be done at the same growth temperature to get a stable Ge 
composition and growth rate. 
One of the key differences between Ge-rich SiGe and Ge growth is that Si atoms 
in the deposition can suppress 3-D growth. A flat initial surface can be achieved in the 
SiGe-on-Si growth at a single growth temperature before annealing, but the 
pure-Ge-on-Si growth requires annealing to reduce the surface roughness, or may even 
require two growth-anneal cycles. 

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(a) (b) 
Figure 3.14: 
[12] 
AFM image of as-grown surface. (a) MBE-grown Ge-on-Si with 
2-growth-temperatures. (b) RPCVD-grown SiGe-on-Si at a single growth temperature. Both samples 
were annealed 
Fig 3.14 shows the AFM comparison of the Ge-on-Si and SiGe-on-Si samples. Fig 
3.14 (a) shows Ge grown on Si using the two temperature growth method by MBE 
(300/600º
C), it had only 0.2 nm root-mean-square (RMS) roughness. It represents the 
best as-grown surface in the Ge-on-Si case from previous work. Fig 3.14 (b) shows an 
AFM image of the surface of SiGe on Si grown by RPCVD at a single temperature of 
400 º
C with annealing at 850º
C for the first layer and 750º
C for the second layer. The 
silicon concentration is 10%, but the RMS roughness is also 0.2nm after the annealing. 
If Ge is grown under the same conditions, the RMS roughness will be 25nm. The 
surface roughness shown in Fig 3.14(b) increases to 1~2 nm with longer annealing 
time and higher temperature. 
Previous work [12] has characterized Si
0.05
Ge
0.95
alloy layers using the single 
temperature growth method. A SiGe layer was deposited on silicon at 400 º
C and then 
annealed at 850º
C; a second SiGe layer was deposited and annealed after that. TEM 
measurements have shown that most threading dislocations have been terminated at 
the Si - SiGe interface. Only a few of them have propagated into the second layer. 
Even though threading dislocations lead to increased dark current, it is still tolerable in 
modulator applications. 

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