Supercomputer

Later developmentsEdit

A new generation of memory card formats, including RS-MMC, miniSD and microSD, feature extremely small form factors. For example, the microSD card has an area of just over 1.5 cm², with a thickness of less than 1 mm.
NAND flash has achieved significant levels of memory density as a result of several major technologies that were commercialized during the late 2000s to early 2010s.
Multi-level cell (MLC) technology stores more than one bit in each memory cell. NEC demonstrated quad-level cell (QLC) technology in 1996, with a 64 Mb flash memory chip storing 2-bit data per cell. STMicroelectronics also demonstrated quad-level cells in 2000, with a 64 Mb NOR flash memory chip.[20] In 2009, Toshiba and SanDisk introduced NAND flash chips with QLC technology storing 4-bit per cell and holding a capacity of 64 Gb. Samsung Electronics introduced triple-level cell (TLC) technology storing 3-bit per cell, and began mass-producing NAND chips with TLC technology in 2010
Charge trap flash (CTF) technology was developed during the 1990s to early 2000s. In 1991, NEC researchers including N. Kodama, K. Oyama and Hiroki Shirai described a type of flash memory with a charge trap method.[24] In 1998, Boaz Eitan of Saifun Semiconductors (later acquired by Spansion) patented a flash memory technology named NROM that took advantage of a charge trapping layer to replace the floating gate used in conventional flash memory designs In 2000, an Advanced Micro Devices (AMD) research team led by Richard M. Fastow, Egyptian engineer Khaled Z. Ahmed and Jordanian engineer Sameer Haddad (who later joined Spansion) demonstrated a charge-trapping mechanism for NOR flash memory cells.[26] CTF was later commercialized by AMD and Fujitsu in 2002 3D V-NAND (vertical NAND) technology stacks NAND flash memory cells vertically within a chip using 3D charge trap flash (CTP) technology. 3D V-NAND technology was first announced by Toshiba in 2007 and was first commercially released by Samsung Electronics in 2013
3D integrated circuit (3D IC) technology stacks integrated circuit (IC) chips vertically into a single 3D IC chip package Toshiba introduced 3D IC technology to NAND flash memory in April 2007, when they debuted a 16 GB THGAM embedded NAND flash memory chip, which was manufactured with eight stacked 2 GB NAND flash chips.[31] In September 2007, Hynix Semiconductor (now SK Hynix) introduced 24-layer 3D IC technology, with a 16 GB flash memory chip that was manufactured with 24 stacked NAND flash chips using a wafer bonding process Toshiba also used an eight-layer 3D IC for their 32 GB THGBM flash chip in 2008 In 2010, Toshiba used a 16-layer 3D IC for their 128 GB THGBM2 flash chip, which was manufactured with 16 stacked 8 GB chips. In the 2010s, 3D ICs came into widespread commercial use for NAND flash memory in mobile devices
As of August 2017, microSD cards with a capacity up to 400 GB (400 billion bytes) are available[ The same year, Samsung combined 3D IC chip stacking with its 3D V-NAND and TLC technologies to manufacture its 512 GB KLUFG8R1EM flash memory chip with eight stacked 64-layer V-NAND chips In 2019, Samsung produced a 1 TB flash chip, with eight stacked 96-layer V-NAND chips and with QLC technology.