Topic 14-15. Cache memory, cache memory functions and levels. 14-15-Mavzu. Kesh xotira, kesh xotira vazifalari va darajalari

Memory build hierarchical scheme

Fast memory (RAM)
3-level cache (L3)
2-level cache (L2)
Step 1 instructions cache (L 1 I)
Level 1 data cache (L 1 D)
Registers

Xotirani qurishning iyerarxik sxemasi

Tezkor xotira (RAM)
3-sath kesh (L3)
2-sath kesh (L2)
1-sath ko’rsatmalar keshi (L1I)
1-sath ma’lumotlar keshi (L1D)
Registrlar

Processor between the core , cache and TSQ reciprocal contacts formed reach scheme :

Processor between the core , cache and TSQ reciprocal contacts formed reach scheme :

Prorsessor yadrosi, kesh va TSQ o’rtasidagi o’zaro aloqlarni tashkil etish sxemasi:

Prorsessor yadrosi, kesh va TSQ o’rtasidagi o’zaro aloqlarni tashkil etish sxemasi:

To the cache write methods

Data cache _ write two basic method available :

• write-back method ( reverse write ) - data first in turn to the cache , then some a conditions appear when To TSQ is written .
• write-through method ( from the beginning to the end write skvoznaya zapis) - data write a of time in itself and in the TSQ raw in the cache instead is increased .

Keshga yozish usullari

Ma’lumotlarni kesh-xotiraga yozishning ikkita asosiy usuli mavjud:

• write-back usuli (teskari yozish) – ma’lumotlar birinchi navbatda keshga, so’ngra ba’zi bir shartlar paydo bo’lganda TSQga yoziladi.
• write-through usuli (boshidan oxirigacha yozish сквозная запись) – ma’lumotlarni yozish bir vaqtning o’zida xam TSQ da va xam keshda amalga oshiriladi.

Processor cache _ levels

Protsessorning kesh-xotira darajalari

Cache memory associativity architecture

Caching associativity architecture for following basic options available :

• Straight described cache - TSQ known a field for of the cache detected known a field responsible
• Exactly associative cache - of the cache optional field Of TSQ optional field with connection possible
• Mixed cache ( associative package )