Motivation The silicon strip tracker of atlas upgrade


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Motivation



HL-LHC: 10x increase of luminosity wrt LHC (~1035 cm-2·s-1)

  • HL-LHC: 10x increase of luminosity wrt LHC (~1035 cm-2·s-1)

    • More events on the detectors => Higher hit density
      • Faster detectors and electronics
      • More channels => Higher power demands, material budget constraints, space for services limited
      • New powering schemes for on-detector electronics
    • ATLAS ID has to be redesigned and rebuilt completely
      • Silicon tracker: upgraded tracker for the ATLAS detector
        • Inner tracker: Si pixel detector
        • Outer tracker: Si strips tracker


Si strip sensors arranged in double-sided layers of “staves” (barrel) and “petals” (end-caps)

  • Si strip sensors arranged in double-sided layers of “staves” (barrel) and “petals” (end-caps)

  • Numerous sensor modules per stave and petal side:



Sensor module prototypes:

  • Sensor module prototypes:

      • Strip sensor (2.5 (SS) & 10 (LS) cm barrel, 2.7 to 5.4 cm endcaps)
      • Readout hybrids (10 ROICs + 1 HCC/hybrid)
      • Readout chip: ABC-Next (130 nm CMOS)
        • Binary readout
        • 256 channels/ABCN
          • Power consumption estimates: ~ 250 mW/ABCN (< 1mW /ch)[1]
          • Analogue (1.2 V): ~ 280 μW/ch
          • Digital (0.9 V): ~ 360 μW/ch
      • Hybrid Controller Chip (HCC)
        • Power consumption estimations: ~ 180 mW (0.9 V) [2]
      • Still a “conceptual” idea
        • Current prototypes under test are with ACBn25
        • ASICs (250 nm CMOS, 128 channels/chip):


Independent powering (as in SCT)

  • Independent powering (as in SCT)

  • Serial powering

  • DC-DC powering



    • Constant current along the chain, equal to the hybrid current
    • Shunt transistors and low-dropout regulators (LDOs) provide hybrid voltage
      • Shunt regulator shunts excessive hybrid current, “recycled” in the serial power line
      • LDOs derive locally analogue/digital voltage in the ABCns
      • Several possible configurations
    • Each module at a different ‘GND’  AC coupling required for control and data lines
    • Is = Ih (constant)
    • Vs = n·Vh


    • Parallel powering of each module
    • 2-step voltage conversion:
      • 1st step: Buck DC-DC converters (1 per module)
        • Inductor as energy storage unit and switch power transistors
        • Voltage conversion ratio = g (typically between 4 and 6)
      • 2nd step: Step-down switched capacitors (1 or 2 per ABCN)
        • Voltage conversion ratio = w (typically 2 – 2.5)
      • Total conversion ratio = r = g·w (typically between 8 and 10)
    • IS = n·(Ih/r) = n·(Ih/(g·w))
    • VS = r·VABCn (constant)
    • 2nd step may not be possible on-chip due to noise on ABCn internal power buses coming from switched caps
      • Currently under investigation


Module prototypes built and being tested with both power configurations:

  • Module prototypes built and being tested with both power configurations:

    • Individual modules:
      • Liverpool (SP & DC-DC)
      • Berkeley Lab (SP)
      • Geneva (DC-DC)
      • Oxford (SP)
      • BNL (SP)
      • Cambridge, Santa Cruz,
      • DESY, Freiburg, Glasgow, …
    • “Stavelet”:
      • RAL (SP)
    • Under construction:
      • DC-DC powered stavelets
      • “Petalet” (endcaps)


Barrel modules:

  • Barrel modules:

    • Serial powering:
      • Analogue voltage derived from shunts, digital from LDOs
      • Shunt regulator efficiency = 85% [3]
      • LDOs dropout voltage = 0.3 V
      • Estimated ε = 69 % (no trace/cable losses)
      • Total power per stave = 62 W
    • DC-DC powering:
      • 1st step (buck converters) delivers 2.4 V
      • 2nd step (switched caps) delivers 1.2 - 0.9 V
      • Buck converters efficiency = 85% [4]
      • Simulated switched caps efficiency = 97% [5]
      • Estimated ε = 82 % (no trace/cable losses)
      • Total power per stave = 53 W


Endcap modules

  • Endcap modules

    • Non uniform within the same petal
      • Different hybrid and sensor sizes  different capacitive loads
    • Serial powering:
      • ε = 56% (no trace/cable losses)[6]
      • Total power per petal = 30.7 W
      • Current in the line defined by the
      • biggest hybrid (10 ABCns)
      • High LDO losses
    • DC-DC powering:
      • ε = 78% (no trace/cable losses)[6]
      • Total power per petal = 22.3 W


Results with latest ABCN250 stave module and stavelet prototypes from Liverpool, RAL and Geneva

  • Results with latest ABCN250 stave module and stavelet prototypes from Liverpool, RAL and Geneva

    • Evidences of (low) noise signatures related to powering in the modules
    • Similar input noise both for serial and DC-DC with current module prototypes: ~ 600 – 615 e at 1 fC [7]
      • No additional noise introduced by serial power protection circuit
      • EM noise from inductors and switching noise minimized with optimized shielding (Cu tape) for DC-DC
    • Serially and DC-DC powered stavelets show no additional noise wrt individual modules [8]


Serial powering:

  • Serial powering:

    • Need to protect serial power chain in case of open circuit, noisy module, …
    • Power Protection Board (PPB) + Serial Power Interface (SPi) allow slow-control and real time bypass modules within a SP chain
    • Designed, fabricated, and successfully tested with RAL stavelet[9]:
    • SPP ASIC currently under design, to be submitted this year
  • DC-DC powering:

    • Protection components implemented in buck converter ASIC prototype (AMIS4, submitted Jan 2011)[10]
      • Over current, over temperature, input under-voltage
      • Soft start state machine for reliable start-up procedure


Last material estimations for ABCN130 short strips stave module[11]:

  • Last material estimations for ABCN130 short strips stave module[11]:

  • Serial powering:

    • 1 control and 1 protection ASIC/hybrid, shunts, included
    • Bus traces not included
      • % X0 = 0.03 to stave, coming from extra hybrid area and AC-coupling caps
        • Assuming 10% higher power dissipation for serial than DC-DC on the stave: effect on (as-built) stave core ~ 0.02% /0.01% additional from StSt/Ti cooling pipes
  • DC-DC:

    • Buck ASIC, PCB (Cu), custom inductor (Cu), inductor Shielding (Cu), included
    • Switched capacitors not included
    • Bus traces for DC-DC power not included
      • % X0 = 0.23 to stave, coming from capacitors, buck PCB, inductor and shield
        • This number could be reduced by the use of Al instead of Cu on several components of the buck converter, studies underway


LV cable needs:

  • LV cable needs:

    • DC-DC powering:
      • 1 power line per stave, ~ 5 A for short strips
      • End of Stave (EoS) boards included in the power scheme
    • Serial powering:
      • 1 power line per stave ~ 2 A for short strips
      • EoS boards not included in the serial power chain
        • Additional power line ~ 0.8 A
  • Two possible reuse scenarios, both of them feasible in principle:

    • Scenario 1: Reuse SCT cables
    • Scenario 2: Reuse TRT Cables
      • Enough Cu cross-section, but cable count not sufficient
        • Need to redistribute Cu cross-section
    • ONLY LV cables considered here!




Backup slides

  • Backup slides









LV cable needs:

  • LV cable needs:




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