Original concept

Original concept

Various older (EPROM) PIC microcontrollers

The original PIC was intended to be used with General Instrument's new CP1600 16-bit central processing unit (CPU). The CP1600 was a powerful processor for its era, implementing most of the PDP-11 minicomputer's instruction set architecture in a microcomputer package.

Whilst most people considered the CP1600 a good CPU, it had one significant problem; to reduce pin count of its physical DIP packaging, the address bus and data bus shared pins. For CPUs that had separate I/O channels, like the Intel 8008, this would not have been a problem, but the 1600 also used the PDP-11's memory mapped input/output concept. This meant that communicating with a device required the device to watch for key memory locations being accessed on one machine cycle, and then read the data on the next. This made I/O on the machine slower as the bus alternated between address and data modes, and more expensive to implement as the devices had to latch inputs over multiple cycles. All of this complexity was repeated on the CPU side in the corresponding device driver.

To address this shortcoming of the 1600, the 8-bit PIC was developed in 1975. The idea was that a system would have one or more of the low-cost PICs performing the actual I/O with the devices, and then sending that data to the CPU. The PIC used simple microcode stored in ROM to perform its tasks, and although the term RISC was not used at the time, it shares some common features with RISC designs.

After the 1600

In 1985, General Instrument sold their microelectronics division and the new owners cancelled almost everything which by this time was mostly out-of-date. The PIC, however, was upgraded with an internal EPROM to produce a programmable channel controller. At the same time Plessey in the UK released NMOS processors numbered PIC1650 and PIC1655 based on the GI design, using the same instruction sets, either user mask programmable or versions pre-programed for auto-diallers and keyboard interfaces. ^[6]

In 1998 Microchip introduced the PIC 16F84, a flash programmable and erasable version of its successful serial programmable PIC16C84 In 2001, Microchip introduced more Flash programmable devices, with full production commencing in 2002. [2]

Today, a huge variety of PICs are available with various on-board peripherals (serial communication modules, UARTs, motor control kernels, etc.) and program memory from 256 words to 64K words and more (a "word" is one assembly language instruction, varying in length from 8 to 16 bits, depending on the specific PIC micro family).

PIC and PICmicro are now registered trademarks of Microchip Technology. It is generally thought that PIC stands for Peripheral Interface Controller, although General Instruments' original acronym for the initial PIC1640 and PIC1650 devices was "Programmable Interface Controller".^[4] The acronym was quickly replaced with "Programmable Intelligent Computer".^[5]

The Microchip 16C84 (PIC16x84), introduced in 1993, was the first^[7] Microchip CPU with on-chip EEPROM memory.

By 2013, Microchip was shipping over one billion PIC microcontrollers every year.^[8]

Device families

PIC micro chips are designed with a Harvard architecture, and are offered in various device families. The baseline and mid-range families use 8-bit wide data memory, and the high-end families use 16-bit data memory. The latest series, PIC32MZ is a 32-bit MIPS-based microcontroller. Instruction words are in sizes of 12-bit (PIC10 and PIC12), 14-bit (PIC16) and 24-bit (PIC24 and dsPIC). The binary representations of the machine instructions vary by family and are shown in PIC instruction listings.

Within these families, devices may be designated PICnnCxxx (CMOS) or PICnnFxxx (Flash). "C" devices are generally classified as "Not suitable for new development" (not actively promoted by Microchip). The program memory of "C" devices is variously described as OTP, ROM, or EEPROM. As of October 2016, the only OTP product classified as "In production" is the pic16HV540. "C" devices with quartz windows (for erasure), are in general no longer available.

PIC10 and PIC12

Further information on this family of microcontrollers: PIC instruction listings § Baseline core devices (12-bit)

These devices feature a 12-bit wide code memory, a 32-byte register file, and a tiny two level deep call stack. They are represented by the PIC10 series, as well as by some PIC12 and PIC16 devices. Baseline devices are available in 6-pin to 40-pin packages.

Generally the first 7 to 9 bytes of the register file are special-purpose registers, and the remaining bytes are general purpose RAM. Pointers are implemented using a register pair: after writing an address to the FSR (file select register), the INDF (indirect f) register becomes an alias for the addressed register. If banked RAM is implemented, the bank number is selected by the high 3 bits of the FSR. This affects register numbers 16–31; registers 0–15 are global and not affected by the bank select bits.

Because of the very limited register space (5 bits), 4 rarely read registers were not assigned addresses, but written by special instructions (OPTION and TRIS).

The ROM address space is 512 words (12 bits each), which may be extended to 2048 words by banking. CALL and GOTO instructions specify the low 9 bits of the new code location; additional high-order bits are taken from the status register. Note that a CALL instruction only includes 8 bits of address, and may only specify addresses in the first half of each 512-word page.

Lookup tables are implemented using a computed GOTO (assignment to PCL register) into a table of RETLW instructions.

This "baseline core" does not support interrupts; all I/O must be polled. There are some "enhanced baseline" variants with interrupt support and a four-level call stack.

PIC10F32x devices feature a mid-range 14-bit wide code memory of 256 or 512 words, a 64-byte SRAM register file, and an 8-level deep hardware stack. These devices are available in 6-pin SMD and 8-pin DIP packages (with two pins unused). One input only and three I/O pins are available. A complex set of interrupts are available. Clocks are an internal calibrated high-frequency oscillator of 16 MHz with a choice of selectable speeds via software and a 31 kHz low-power source.

PIC16

Further information on this family of microcontrollers: PIC instruction listings § Mid-range core devices (14 bit), and PIC instruction listings § Enhanced mid-range core devices (14 bit)

Microchip PIC16C58A

These devices feature a 14-bit wide code memory, and an improved 8-level deep call stack. The instruction set differs very little from the baseline devices, but the two additional opcode bits allow 128 registers and 2048 words of code to be directly addressed. There are a few additional miscellaneous instructions, and two additional 8-bit literal instructions, add and subtract. The mid-range core is available in the majority of devices labeled PIC12 and PIC16.

The first 32 bytes of the register space are allocated to special-purpose registers; the remaining 96 bytes are used for general-purpose RAM. If banked RAM is used, the high 16 registers (0x70–0x7F) are global, as are a few of the most important special-purpose registers, including the STATUS register which holds the RAM bank select bits. (The other global registers are FSR and INDF, the low 8 bits of the program counter PCL, the PC high preload register PCLATH, and the master interrupt control register INTCON.)

The PCLATH register supplies high-order instruction address bits when the 8 bits supplied by a write to the PCL register, or the 11 bits supplied by a GOTO or CALL instruction, is not sufficient to address the available ROM space.