· Product price is reduced

Today, programmable logic integrated circuits (FPGAs) are increasingly being used in a variety of modern devices because FPGA has significant advantages over traditional digital chips. These benefits include:
· The time characteristics of the product are improved.
· Product price is reduced.
· Product dimensions are reduced.
Product reliability is increased (number of discrete chips is reduced)
Increases product flexibility (FPGA can always be reprogrammed)
The FPGA architecture has a complex structure (Figure 1)
Figure 1. Internal structure of FPGA
As shown in Figure 1, the main part of the FPGA consists of programmable logic blocks and programmable internal links.
The FPGA programming (firmware) process itself consists of creating the necessary connections between the inputs and outputs of the device.
There are two world leaders in FPGA production in the world today. These are the American firms Hilinx and Altera.
Each company offers its own CAD system to work with FPGA. Xilinx offers the Xilinx Software Development Kit (SDK). Altera offers Max + Plus II and Quartus II as well as ModelSim simulation system.
The languages ​​that describe the operation of the hardware are usually used to create software programs, the most common of which are the following languages:
Verilog HDL.

VHDL is the most difficult language to learn, although it has the greatest potential at the functional and behavioral levels of abstraction, but it has fewer capabilities at the structural level of abstraction compared to Verilog HDL. The VITAL library is designed to expand the capabilities of the VHDL language.

Figure 2. Abstraction Levels Verilog and VHDL

An example of a verilog HDL language operation is a program implemented in the CYCLONE III EP3C5E1444C8N FPGA of the Mini-DiLab stand, the general view of which is a form. 3.

Figure 3. General view of the board Mini - DiLab

This program performs serial switching of LED0-led7 LEDs along with control of switching speed using sw0, sw1 switches, in addition to selecting to add “light” movement using pba and pbb buttons.

// Program text
module project (output LED, input clk_25mhz, input pba, input pbb,
input sw);
// Assign project internal links
sim s1;
sim s2;
sims3;
// Invoke other files (subroutines) associated with the project
Tr tr_1 (.out (s2), .set (pba), .res (pbb));
Counter_1 (.q (s1), .clk (clk_25mhz), .up (s2));
Mx mx_1 (.a (s3), .in (s1), .load (sw));
Dc3_8 dc3_8_1 (.out (led), .in (s3));
endmodule // end of program
Tr sub application
module tr (outgoing, installed, res); // Create a program
// Assign inputs / outputs
exit out;
input is set;
input res;
// Start
primary
start
Output <= 1 "d0;
// Basic program code
always @ (set to ignore or ignore res)
start
if (~ (installed))
Output <= 1 "d1;
other
Output <= 1 "d0;
endmodule // Program end
The opposite program
module counter (con, q, clk, up); // Start the program
output con;
output q \ u003d con;
input up, clk;
// Basic program code
always @ (put clk)
start
agar (clk)
if (up)
Con <= con - 1 "d1;
other
Con <= con + 1 "d1;
endmodule // End of program
Mx subroutin (multiplexer)
module mx (output reg a, input, input load);
// Basic program code
always @ *
start
work (cargo)
2 "b00: a \ u003d in;
2 "b01: a \ u003d in;
2 "b10: a \ u003d in;
2 "b11: a \ u003d in;
last letter
endmodule // Program end
DC3_8 subroutine (multiplexer)
module dc3_8 (outside, inside); // Start the program
// Assign inputs / outputs
exit reg out;
in the input wire;
// Basic program code
always @ *
start
work (inside)

3 "d0: out \u003d 8" b11111110;

3 "d1: out \u003d 8" b11111101;

3 "d2: out \u003d 8" b11111011;

3 "d3: out \u003d 8" b11110111;

3 "d4: out \u003d 8" b11101111;

3 "d5: out \u003d 8" b11011111;

3 "d6: out \u003d 8" b10111111;

3 "d7: out \u003d 8" b01111111;

last letter

endmodule // Program end

The program was implemented in CAD Quartus II.

After compiling the program, the compiler did not make any mistakes or comments regarding the program separation and syntax in the program.

Figure 4. Project Messages window

The comments provided by the developer indicate the lack of a license for Quartus II (the free version of the program was used for training) and the lack of files needed to model the project.

RTL The structure of this project is shown in Figs. 5.

Figure 6. Part of the FPGA involved in the project

Conclusion: Programmable logic integrated circuits are useful in many devices. To learn how to work with them, familiarity with equipment description languages ​​(Verilog HDL and VHDL) should be included in the curriculum of specialties related to the design and construction of radio electronic equipment.

The principle of operation of FPGA

FPGA is the same typical ASIC that consists of the same transistors used to assemble flip-flops, registers, multiplexers, and other logic gates for traditional circuits. Of course, you cannot change the connection order of these transistors. But from an architectural point of view, the chips are built with so much subtlety that you can change the signal exchange between large blocks: they are called CLB - programmable logic blocks.

You can also change the logic function that the CLB performs. This is achieved because all chips are embedded with Static RAM configuration memory cells. Each bit of this memory controls any signal switch or is part of a logical function truth table that the CLB performs.

Because the configuration memory is built using Static RAM technology, firstly, when the FPGA is enabled, the chip needs to be configured, and secondly, the chip can be reconfigured almost infinitely many times.

Very simplified 2D IC structure without configuration memory

CLBs are located in the key matrix that defines the I / O connections of CLBs.

Switching matrix diagram

At each intersection of the conductors there are six toggle switches controlled by their configuration memory cells. By opening some and closing others, you can ensure that different signals are exchanged between CLBs.

CLB

A CLB is very simply a block that defines a logical function (called a Look Up Table, LUT) and a trigger (flip-flop, FF) consisting of several arguments. Modern FPGAs have six inputs in the LUT, but for simplicity, the figure shows three. The LUT is supplied to the CLB output asynchronously (directly) or synchronously (via the FF flip-flop running on the system clock).

The principle of implementation of LUT

It is interesting to look at the principle of implementation of LUT. We have a logical function y \ u003d (a & b) | if ~ c. Its schematic representation and reality table are shown in the figure. The function has three arguments, so it takes the value 2 ^ 3 \ u003d 8. Each corresponds to a specific combination of input signals. These values ​​are calculated by the FPGA firmware development program and written to special cells in the configuration memory.