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Төмендегі әр тапсырма бал:

1. 
   Келесі C тіліндегі кода фрагментін MIPS ауыстырыңыз:
   

If (t0 < 0) then t7 = 0 – t0 else t7 = t0;

2. 
   Бір өлшемді массив элементтері ішінен екі рет қайталанатын сандарды өшір.
   

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Программалық инженерия кафедрасы « 22 » 11 .2022ж
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Емтихан билеті №
Төмендегі тест сұрақтарынан дұрыс нұсқасын бояңыз және дұрыс жауаптарды кестеге толтырыңыз. әрбір сұрақ 1,8 бал:

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1. What is the name of the connector for installing the CPU?
a) USB
b) Socket
c) Port
d) PSI
2. For x86 processors, the architecture is used
a) CISC architecture
b) SRS architecture
c) LRM architecture
d) ARM architecture
3. We have 32-bit addresses, four set direct mapped cache, 64-byte block size. How many bits are in the Offset?

A) 2

B) 4

C) 6

D) 1

4. How is the cache memory data block organized in the I486 microprocessor?

A) 4 directions of 128 sets

B) 2 directions of 64 sets

C) 1 block of 128 lines

D) 1 block of 256 lines

5. Which of the following methods bypasses the CPU for data transfer?
A. Software interrupt
B. Interrupt driven I/O
C. Polled I/O
D. Direct Memory Access (DMA)
6. What is the fastest memory in a computer?
A. RAM
B. Cache memory
C. Processor register memory
D. Hard drives
7. If a memory load address hits in both the store buffer and the cache, which one do we use?
a) Cache
b) Speculative Store Buffer
c) Either
d) None of them

8. How many Floating Point operations are occurring per cycle in this example?
a)0.05
b)0.111
c)0.125
d)0.120
9. Are VLIW EQ and VLIW LEQ scheduling and hardware models?
a) No, just scheduling models.
b) Yes, the both models
c) Only hardware models.
d) They’re not a model.
10. Are VLIW EQ and VLIW LEQ is a hardware?
a) Yes, They’re actually something that’s in hardware
b) No, They're not actually something that's in the hardware
c) Only VLIW EQ something that’s in hardware
d) Only VLIW LEQ something that’s in hardware
11. A large number of registers requires more bits to specify the register as an operand in the instruction, which leads to
a) increase redundancy
b) to increase the size of the code.
c) for reduce the size of the code
d) slower operation
12. Are VLIW EQ and VLIW LEQ scheduling and hardware models?
a) No, just scheduling models.
b) Yes, the both models
c) Only hardware models.
d) They’re not a model.
13. For a six-stage pipelining, the initial instruction requires-------cycle for execution?
A)1 cycle
B)3 cycle
C)6 cycle
D)5 cycle.
14. ARM processors are available in the form of -------- pipelining?
A)3 stage
B)5 stage
D)8 stage
C)No one.
15. Which of these UML diagrams are likely to be activity part of the process view?
a) to activity diagram
b) the state diagram
c) a class diagram
d) the sequence diagram
16. To which view would the developed Package Diagram belong? Remember that a package diagram shows the packages that make up a software and how they are related.
a) process view
b) logical view
c) development view
d) physical view
17. Which Algorithm is a better choice for pipelining?
a) Small Algorithm
b) Hash Algorithm
c) Merge-Sort Algorithm
d) Fermat's Algorithm
18. The expression 'delayed load’ is used in context of
a) processor-printer communication
b) memory-monitor communication
c) to the pipelining
d) none of the above
19. How does the MESI protocol work?
A) The protocol works without interacting with the cache
B) To protocol works by having each cache keep track of the state of the data it has.
C) The protocol works by loading the entire cache
D) Only protocol works by preventing the entire cache from monitoring the status of existing data.
20. How does snooping works with a shared bus and multiple processors?
A) When multiple processors are sharing a bus, they will each have their own cache. In order for the caches to stay consistent, they need to communicate with each other. This is done through a process called snooping.
B) When one cache wants to read or write to a place on the bus, it waits for someone to let it.
C) The other caches in the bus will check which one is in charge.
D) They just ignore each other’s signals.
21. Flow control are have two ways, which ?
a) (CTS/RTS) && (XOn/XOff)
b) (TCP/IP) && TCP
c) HTTPS && HTTP
d) CDN && СВТО
22. What happens as a result of a deadlock?
a) the program stops working
b) to all programs stop working
c) an resource break programs and cycles
d) the cache is restarted while cycles is not

Compiled by _

K. Margulan