Bit
|
Attr
|
Reset Value
|
Description
|
15
|
W1C
|
0x0
|
AIS
Abnormal Interrupt Summary
Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Register OP_MODE:
Register GMAC_STATUS[1]: Transmit Process Stopped
Register GMAC_STATUS[3]: Transmit Jabber Timeout
Register GMAC_STATUS[4]: Receive FIFO Overflow
Register GMAC_STATUS[5]: Transmit Underflow
Register GMAC_STATUS[7]: Receive Buffer Unavailable
Register GMAC_STATUS[8]: Receive Process Stopped
Register GMAC_STATUS[9]: Receive Watchdog Timeout
Register GMAC_STATUS[10]: Early Transmit Interrupt
Register GMAC_STATUS[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit.
This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be
set is cleared.
|
14
|
W1C
|
0x0
|
ERI
Early Receive Interrupt
This bit indicates that the DMA had filled the first data buffer of the packet. Receive Interrupt Register GMAC_STATUS[6] automatically clears this bit.
|
13
|
W1C
|
0x0
|
FBI
Fatal Bus Error Interrupt
This bit indicates that a bus error occurred, as detailed in [25:23]. When this bit is set, the corresponding DMA engine disables all its bus accesses.
|
12:11
|
RO
|
0x0
|
reserved
|
10
|
W1C
|
0x0
|
ETI
Early Transmit Interrupt
This bit indicates that the frame to be transmitted was fully transferred to the MTL Transmit FIFO.
|
