Chapter 41 gmac ethernet Interface

Filter i Offset

This register defines the offset (within the frame) from which the frames are examined by filter i. This 8-bit pattern-offset is the offset for the filter i first byte to examined. The minimum allowed is 12, which refers to the 13th byte of the frame (offset value 0 refers to the first byte of the frame).

Filter i CRC-16

This register contains the CRC_16 value calculated from the pattern, as well as the byte mask programmed to the wake-up filter register block.

7. System Consideration During Power-Down

GMAC neither gates nor stops clocks when Power-Down mode is enabled. Power saving by clock gating must be done outside the core by the CRU. The receive data path must be clocked with clk_rx_i during Power-Down mode, because it is involved in magic packet/wake-on-LAN frame detection. However, the transmit path and the APB path clocks can be gated off during Power-Down mode.

The pmt interrupt is asserted when a valid wake-up frame is received. This interrupt is generated in the clk_rx domain.
The recommended power-down and wake-up sequence is as follows.

1. 
   Disable the Transmit DMA (if applicable) and wait for any previous frame transmissions to complete. These transmissions can be detected when Transmit Interrupt (TI - Register GMAC_STATUS[0]) is received.
   
2. 
   Disable the MAC transmitter and MAC receiver by clearing the appropriate bits in the MAC Configuration register.
   
3. 
   Wait until the Receive DMA empties all the frames from the Rx FIFO (a software timer may be required).
   
4. 
   Enable Power-Down mode by appropriately configuring the PMT registers.
   
5. 
   Enable the MAC Receiver and enter Power-Down mode.
   
6. 
   Gate the APB and transmit clock inputs to the core (and other relevant clocks in the system) to reduce power and enter Sleep mode.
   
7. 
   On receiving a valid wake-up frame, the GMAC asserts the pmt interrupt signal and exits Power-Down mode.
   
8. 
   
   Only
   On receiving the interrupt, the system must enable the APB and transmit clock inputs to the core.
   
9. 
   Read the register GMAC_PMT_CTRL_STA to clear the interrupt, then enable the other modules in the system and resume normal operation.
   

8.