Chmos single-chip 8-bit microcontroller commercial/Express

ABSOLUTE MAXIMUM RATINGS*

^{Ambient Temperature Under Bias .b40}°^{C to a85}°^{C Storage Temperature b65}°^{C to a150}°^C

Voltage on EA/V_PP Pin to V_SS V to ^a13.0V

Voltage on Any Other Pin to V_SS ..^b0.5V to ^a6.5V I_OL Per I/O Pin 15 mA

Power Dissipation. 1.5W

(based on PACKAGE heat transfer limitations, not device power consumption)

*WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability.

OPERATING CONDITIONS

Symbol	Description	Min	Max	Units
TA	Ambient Temperature Under Bias Commercial Express	0 ^b40	^a70 ^a85	°^C °^C
^VCC	Supply Voltage	4.0	6.0	V
	8XC5X-33	4.5	5.5	V
^fOSC	Oscillator Frequency
	8XC5X	3.5	12	MHz
	8XC5X-1	3.5	16	MHz
	8XC5X-2	0.5	12	MHz
	8XC5X-24	3.5	24	MHz
	8XC5X-33	3.5	33	MHz

DC CHARACTERISTICS (Over Operating Conditions)

All parameter values apply to all devices unless otherwise indicated.

Symbol	Parameter	Min	Typ (Note 4)	Max	Unit	Test Conditions
^VIL	Input Low Voltage	^b0.5		0.2 VCC^b0.1	V
^VIL1	Input Low Voltage EA	0		0.2 VCC^b0.3	V
^VIH	Input High Voltage (Except XTAL1, RST)	0.2 VCC^a0.9		VCC^a0.5	V
^VIH1	Input High Voltage (XTAL1, RST)	0.7 VCC		VCC^a0.5	V
^VOL	Output Low Voltage (Note 5) (Ports 1, 2 and 3)			0.3	V	IOL ^e100 mA (Note 1)
				0.45	V	IOL ^e1.6 mA (Note 1)
				1.0	V	IOL ^e3.5 mA (Note 1)
^VOL1	Output Low Voltage (Note 5) (Port 0, ALE, PSEN)			0.3	V	IOL ^e200 mA (Note 1)
				0.45	V	IOL ^e3.2 mA (Note 1)
				1.0	V	IOL ^e7.0 mA (Note 1)
^VOH	Output High Voltage (Ports 1, 2 and 3, ALE, PSEN)	VCC^b0.3			V	IOH ^e^b10 mA
		VCC^b0.7			V	IOH ^e^b30 mA
		VCC^b1.5			V	IOH ^e^b60 mA

DC CHARACTERISTICS (Over Operating Conditions) (Continued) All parameter values apply to all devices unless otherwise indicated.

Symbol	Parameter	Min	Typ (Note 4)	Max	Unit	Test Conditions
^VOH1	Output High Voltage (Port 0 in External Bus Mode)	VCC^b0.3			V	IOH ^e^b200 mA
		VCC^b0.7			V	IOH ^e^b3.2 mA
		VCC^b1.5			V	IOH ^e^b7.0 mA
^IIL	Logical 0 Input Current (Ports 1, 2 and 3)			^b50	mA	VIN ^e0.45V
^ILI	Input leakage Current (Port 0)			^g10	mA	^VIN ^e^VIL ^or VIH
^ITL	Logical 1 to 0 Transition Current (Ports 1, 2 and 3) Commercial Express			^b650 ^b750	mA mA	VIN ^e2V
RRST	RST Pulldown Resistor	40		225	KX
CIO	Pin Capacitance		10		pF	^@^1 MHz, 25°^C
^ICC	Power Supply Current: Active Mode at 12 MHz (Figure 5) at 16 MHz at 24 MHz at 33 MHz (8XC5X-33) Idle Mode at 12 MHz (Figure 5) at 16 MHz at 24 MHz at 33 MHz (8XC5X-33) Power Down Mode 8XC5X-33					(Note 3)
			15	30	mA
			20	38	mA
			28	56	mA
			35	56	mA
			5	7.5	mA
			6	9.5	mA
			7	13.5	mA
			7	15	mA
			5	75	mA
			5	50	mA

NOTES:

1. 
   Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the V_OLs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8V. It may be desirable to qualify ALE or other signals with a Schmitt Triggers, or CMOS-level input logic.
   
2. 
   Capacitive loading on Ports 0 and 2 cause the V_OH on ALE and PSEN to drop below the 0.9 V_CC specification when the address lines are stabilizing.
   
3. 
   See Figures 6 – 9 for test conditions. Minimum V_CC for Power Down is 2V.
   
4. 
   Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
   

and 5V.

5. 
   Under steady state (non-transient) conditions, I_OL must be externally limited as follows: Maximum I_OL per port pin: 10mA
   

Maximum I_OL per 8-bit port—

Port 0: 26 mA

Ports 1, 2 and 3: 15 mA Maximum total I_OL for all output pins: 71 mA

If I_OL exceeds the test condition, V_OL may exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test conditions.

Figure 5. 8XC52/54/58 I_CC vs Frequency

Figure 6. I_CC Test Condition, Active Mode

Figure 7. I_CC Test Condition Idle Mode

Figure 8. I_CC Test Condition, Power Down Mode V_CC ^e 2.0V to 6.0V

Figure 9. Clock Signal Waveform for I_CC Tests in Active and Idle Modes. TCLCH ^e TCHCL ^e 5 ns