High speed, low driving voltage vertical cavity germanium-silicon modulators for optical

1.1.2 On-Chip Interconnects 
Intra-chip interconnects are used for signaling, propagation, and networking on the 
same chip. Fig. 1.2 shows a cross-sectional SEM view of a CMOS chip. Transistors 
are fabricated at the bottom of the multilayer structure. There are local, semi-global 
and global interconnects; metals from different layers are connected by vias. As the 
transistor density kept increasing, the complexity of the interconnect layout and 
number of layers increased as well.
CMOS devices at the bottom of the chip are connected by local and semi-global wires 
in the middle levels and by global wires in the top levels. Because metal wires have 
high resistance and relatively low inductance, the delay of intra-chip interconnects is 
RC-limited, where C is the MOS capacitance in the loading stage, and R could be the 
resistance of metal interconnects, the channel resistance of the MOS device in the 
driving stage, or the combination of both.
Laser

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Figure 1.2 Cross-sectional of a CMOS chip. [13] 
Fig. 1.3 shows the trends of delay versus technology node predicted by the 
International Technology Roadmap for Semiconductors (ITRS). The delays of devices 
and local interconnects are reduced as devices scale, but the delays of global wires 
keep increasing [14]. The key reason why global interconnects cannot share the same 
advantages Moore’s law brings to all other components is because the cross-sectional 
area of wires are reduced with each technology node, but the length is almost the same, 
and hence the resistance and delay increase dramatically. In addition, the skin-depth 
effect at high frequency further increases the resistivity of the wires.
Even though repeaters [15, 16] are used to segment the global wire into several 
shorter sections, the delay cannot be effectively reduced when the technology node 
reaches the sub 50-nm regime. More importantly, the power consumption from 
repeaters increases dramatically. This imposes a serious limitation for future CMOS 
technology to keep using metal global interconnects for signaling and clocking. Low 
power, low cost, integrated optical components need to be developed for future 
interconnects. 

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Figure 1.3 Relative delay versus technology node for gate, local interconnects, and global interconnects 
with and without repeaters