High speed, low driving voltage vertical cavity germanium-silicon modulators for optical

1.1.1 Off-Chip Interconnects 
The term “inter-chip interconnects” normally refers to short range optical 
communication systems with a range of less than 100 meters. That includes last-mile 
transmission, storage area networking and other applications. The interconnect 
hierarchy in the off-chip interconnect domain (< 100m) is typically categorized into 
the following three levels: cabinet level (1 − 100m), backplane level between boards 
(10cm – 1m), chip-to-chip on a board (< 10cm) [8].
There are several reasons why electrical interconnects are commonly used for 
these interconnects: (1) The infrastructure already exists; (2) Low cost deployment (3) 
Speed and signal integrity requirements could previously be satisfied for most 
applications. However, when the signal is transmitted at several gigahertz in electrical 
interconnects, several issues emerge: (1) parasitic effects lead to serious 
electromagnetic interference (EMI) and susceptibility problems, which damage the 
signal integrity; (2) Dielectric material leakage does not scale with the geometry of the 
line; (3) Metal line scaling causes more power consumption (4) The theoretical 
maximum capacity of electrical lines will soon be reached; (5) Signal latency 
increases as the operating frequency increase.
Optical interconnect platforms are providing solutions for 10G Ethernet and 
storage networks [9], board level and chip-to-chip interconnects [10]. Fig 1.1 (a) 
shows the Intel QuickPath architecture as an example of the off-chip optical 
interconnect structure. DRAM is the memory unit, IOH is the input/output hub. This 
architecture is scalable in terms of operating speed and bandwidth [11]. If an efficient 
optical communication solution based on CMOS-compatible processes exists, it will 
be economically viable to be integrated in the core chips (such as chipset or CPU) 
instead of merely to be used for I/O networking chips, and it will eventually be the 
solution for all inter-chip interconnects. [12] Fig 1.1(b) shows the layout of an 

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inter-chip optical interconnect system developed by HP, all the black dies include 
chips, memory units, caches and other computational devices. They are connected by 
an optical communication loop and powered by an off-chip laser. 
Figure 1.1(a) Intel QuickPath interconnect architecture (b) HP layout of the off-chip optical 
interconnect