Appendix D: Sample lesson plan 1
31
Cambridge IGCSE and Cambridge
O Level Computer Science
Appendix D: Sample lesson plan 1
Computer architecture and the fetch execute cycle
Lesson: Computer architecture and
the fetch-execute cycle
School:
Date: Teacher
name:
Class:
Number present:
Absent:
Teaching Aims
• show what happens during the fetch part of the cycle
• show what happens during the
execute part of the cycle
Lesson objectives
• develop understanding of registers and their uses
• develop understanding of the stages of the fetch-execute cycle
Syllabus assessment
objectives
• describe the stages
of the fetch-execute cycle, including the use of
registers
Vocabulary,
terminology and
phrases
Program counter (PC)
Memory Address Register (MAR)
Memory Buffer Register (MBR)
Current Instruction Register (CIR)
Previous learning
• understanding of the basic Von Neumann model for a computer
system and the stored program concept (program
instructions and
data are stored in main memory and instructions are fetched and
executed one after another)
Anticipated learner
problems
• some learners may not understand the previous learning as it is one
of the more challenging
parts of the syllabus
Solutions to the
problems
• use group work to reinforce the principles
• recap and demonstrate using Little Man Computer
Resources
•
http://gcsecomputing.org.uk/lmc/lmc.html
• Diagram used for last lesson showing
Von Neumann architecture
but with names of registers removed
• Cards with stages of the fetch-execute cycle for group work
• Laminated cards to write values
on for register role play
