Zbekiston Respublikasi Oliy ta’lim, fan va innovatsiyalar vazirligi

CHAPTER 3 Modeling of Digital Control Systems



FIGURE 3.1
Common digital control system configuration.



FIGURE 3.2
Ideal sampler model of an ADC.
Clearly, the preceding assumptions are idealizations that can only be approximately
true in practice. Quantization errors are typically small but nonzero; variations
in sampling rate occur but are negligible, and physical ADCs have a finite
conversion time. Nevertheless, the ideal sampler model is acceptable for most
engineering applications.

3.2 DAC model
Assume that
• DAC outputs are exactly equal in magnitude to their inputs.
• The DAC yields an analog output instantaneously.
• DAC outputs are constant over each sampling period.

Then the input-output relationship of the DAC is given by

{u(k)} u(t)=u(k), kT k=0,1,2,… (3.1)
where {u(k)} is the input sequence. This equation describes a zero-order hold
(ZOH), shown in Figure 3.3. Other functions may also be used to construct an
analog signal from a sequence of numbers. For example, a first-order hold constructs
analog signals in terms of straight lines, whereas a second-order hold
constructs them in terms of parabolas.
In practice, the DAC requires a short but nonzero interval to yield an output;
its output is not exactly equal in magnitude to its input and may vary slightly
3.3 The transfer function of the ZOH 57



FIGURE 3.3
Model of a DAC as a zero-order hold.
over a sampling period. But the model of (3.1) is sufficiently accurate for most
engineering applications. The zero-order hold is the most commonly used DAC
model and is adopted in most digital control texts. Analyses involving other hold
circuits are similar, as seen from Problem 3.2.