Bit
|
Attr
|
Reset Value
|
Description
|
22:20
|
RO
|
0x0
|
TS
Transmit Process State
These bits indicate the Transmit DMA FSM state. This field does not generate an interrupt.
3'b000: Stopped; Reset or Stop Transmit Command issued.
3'b001: Running; Fetching Transmit Transfer Descriptor.
3'b010: Running; Waiting for status. 3'b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO).
3'b100: TIME_STAMP write state. 3'b101: Reserved for future use. 3'b110: Suspended; Transmit Descriptor
Unavailable or Transmit Buffer Underflow. 3'b111: Running; Closing Transmit
Descriptor.
|
19:17
|
RO
|
0x0
|
RS
Receive Process State
These bits indicate the Receive DMA FSM state. This field does not generate an interrupt.
3'b000: Stopped: Reset or Stop Receive Command issued.
3'b001: Running: Fetching Receive Transfer Descriptor.
3'b010: Reserved for future use.
3'b011: Running: Waiting for receive packet. 3'b100: Suspended: Receive Descriptor Unavailable.
3'b101: Running: Closing Receive Descriptor. 3'b110: TIME_STAMP write state.
3'b111: Running: Transferring the receive packet data from receive buffer to host
memory.
|
Only
T-chip
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