Bit
|
Attr
|
Reset Value
|
Description
|
9
|
W1C
|
0x0
|
RWT
Receive Watchdog Timeout
This bit is asserted when a frame with a length greater than 2,048 bytes is received.
|
8
|
W1C
|
0x0
|
RPS
Receive Process Stopped
This bit is asserted when the Receive Process enters the Stopped state.
|
7
|
W1C
|
0x0
|
RU
Receive Buffer Unavailable
This bit indicates that the Next Descriptor in the Receive List is owned by the host and cannot be acquired by the DMA. Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, Receive Process resumes when the next recognized incoming frame is received. Register GMAC_STATUS[7] is set only when the previous Receive Descriptor was owned by the DMA.
|
6
|
W1C
|
0x0
|
RI
Receive Interrupt
This bit indicates the completion of frame reception. Specific frame status information has been posted in the descriptor. Reception remains in the Running state.
|
5
|
W1C
|
0x0
|
UNF
Transmit Underflow
This bit indicates that the Transmit Buffer had an Underflow during frame transmission.
Transmission is suspended and an Underflow
Error TDES0[1] is set.
|
4
|
W1C
|
0x0
|
OVF
Receive Overflow
This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to application, the overflow status is set in RDES0[11].
|
