Bit
|
Attr
|
Reset Value
|
Description
|
15
|
RW
|
0x0
|
PS
Port Select
Selects between GMII and MII: 1'b0: GMII (1000 Mbps)
1'b1: MII (10/100 Mbps)
|
14
|
RW
|
0x0
|
FES
Speed
Indicates the speed in Fast Ethernet (MII) mode:
1'b0: 10 Mbps
1'b1: 100 Mbps
|
13
|
RW
|
0x0
|
DO
Disable Receive Own
When this bit is set, the GMAC disables the reception of frames when the gmii_txen_o is asserted in Half-Duplex mode.
When this bit is reset, the GMAC receives all packets that are given by the PHY while
transmitting.
|
12
|
RW
|
0x0
|
LM
Loopback Mode
When this bit is set, the GMAC operates in loopback mode at GMII/MII. The (G)MII Receive clock input (clk_rx_i) is required for the loopback to work properly, as the
Transmit clock is not looped-back internally.
|
11
|
RW
|
0x0
|
DM
Duplex Mode
When this bit is set, the GMAC operates in a Full-Duplex mode where it can transmit and receive simultaneously. This bit is RO with default value of 1'b1 in Full-Duplex-only configuration.
|
Only
T-chip
Bit
|
Attr
|
Reset Value
|
Description
|
10
|
RW
|
0x0
|
IPC
Checksum Offload
When this bit is set, the GMAC calculates the 16-bit one's complement of the one's complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 25-26 or 29-30 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The GMAC core also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected).
When this bit is reset, this function is disabled. When Type 2 COE is selected, this bit, when set, enables IPv4 checksum checking for received frame payloads TCP/UDP/ICMP headers. When this bit is reset, the COE function in the receiver is disabled and the corresponding PCE and IP HCE status bits are
always cleared.
|
9
|
RW
|
0x0
|
DR
Disable Retry
When this bit is set, the GMAC will attempt only 1 transmission. When a collision occurs on the GMII/MII, the GMAC will ignore the current frame transmission and report a Frame Abort with excessive collision error in the transmit frame status.
When this bit is reset, the GMAC will attempt
retries based on the settings of BL.
|
8
|
RW
|
0x0
|
LUD
Link Up/Down
Indicates whether the link is up or down during the transmission of configuration in RGMII interface:
1'b0: Link Down
1'b1: Link Up
|
Only
T-chip
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