Bit
|
Attr
|
Reset Value
|
Description
|
31
|
RW
|
0x0
|
RA
Receive All
When this bit is set, the GMAC Receiver module passes to the Application all
frames received irrespective of whether they pass the address filter. The result of the SA/DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes to the Application only those
frames that pass the SA/DA address filter.
|
30:11
|
RO
|
0x0
|
reserved
|
10
|
RW
|
0x0
|
HPF
Hash or Perfect Filter
When set, this bit configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by HMC or HUC bits. When low and if the HUC/HMC bit is set, the frame is passed only if it matches the Hash filter.
|
9
|
RW
|
0x0
|
SAF
Source Address Filter Enable
The GMAC core compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison matches, then the SAMatch bit of RxStatus Word is set high. When this bit is set high and the SA filter fails, the GMAC drops the frame. When this bit is reset, then the GMAC Core forwards the received frame to the application and with the updated SA Match bit of the RxStatus depending on the SA address comparison.
|
8
|
RW
|
0x0
|
SAIF
SA Inverse Filtering
When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers will be marked as failing the SA Address filter.
When this bit is reset, frames whose SA does not match the SA registers will be marked as
failing the SA Address filter.
|
