Chapter 41 gmac ethernet Interface


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Bit

Attr

Reset Value

Description

31:6

RO

0x0

reserved

5


RW


0x0


FHP
Full-Half preset
When low and bit4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half - 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half - 16)
When high and bit4 is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (full - 2KBytes) and all frame-counters gets preset
to 0xFFFF_FFF0 (full - 16)

4

R/WSC

0x0

CP
Counters Preset
When set, all counters will be initialized or preset to almost full or almost half as per Bit5 above. This bit will be cleared automatically after 1 clock cycle. This bit along with bit5 is useful for debugging and testing the assertion of interrupts due to MMC counter becoming half-full or full.




Bit

Attr

Reset Value

Description

3

RW

0x0

MCF
MMC Counter Freeze
When set, this bit freezes all the MMC counters to their current value. (None of the MMC counters are updated due to any transmitted or received frame until this bit is reset to 0. If any MMC counter is read with the Reset on Read bit set, then that counter is also
cleared in this mode.)

2


RW


0x0


ROR
Reset on Read
When set, the MMC counters will be reset to zero after Read (self-clearing after
reset). The counters are cleared when the least significant byte lane (bits[7:0]) is
read.

1


RW


0x0


CSR
Counter Stop Rollover
When set, counter after reaching maximum value will not roll over to zero

0

R/WSC

0x0

CR
Counters Reset
When set, all counters will be reset. This bit will be cleared automatically after 1
clock cycle


Only

T-chip
GMAC_MMC_RX_INTR


Address: Operational Base + offset (0x0104) MMC Receive Interrupt Register


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