Bit
|
Description
|
31
|
Disable Interrupt on Completion
When set, this bit will prevent the setting of the RI (CSR5[6]) bit of the GMAC_STATUS Register for the received frame that ends in the buffer pointed to by this descriptor.
This, in turn, will disable the assertion of the interrupt to Host due to RI for that frame.
|
30:26
|
Reserved.
|
25
|
RER: Receive End of Ring
When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns to the base address of the list, creating a Descriptor Ring.
|
24
|
RCH: Second Address Chained
When set, this bit indicates that the second address in the descriptor is the Next Descriptor address rather than the second buffer address. When RDES1[24] is set, RBS2 (RDES1[21-11]) is a “don’t care” value.
RDES1[25] takes precedence over RDES1[24].
|
23:22
|
Reserved.
|
21:11
|
RBS2: Receive Buffer 2 Size
These bits indicate the second data buffer size in bytes. The buffer size must be a multiple of 8 depending upon the bus widths (64), even if the value of RDES3 (buffer2 address pointer) is not
aligned to bus width. In the case where the buffer size is not a multiple of 8, the resulting behavior is undefined. This field is not valid if RDES1[24] is set.
|
10:0
|
RBS1: Receive Buffer 1 Size
Indicates the first data buffer size in bytes. The buffer size must be a multiple of 8 depending upon the bus widths (64), even if the value of RDES2 (buffer1 address pointer) is not aligned. In the case where the buffer size is not a multiple of 8, the resulting behavior is undefined. If this field is 0, the DMA ignores this buffer and uses
Buffer 2 or next descriptor depending on the value of RCH (Bit 24).
|
