Introduction to Parallel Processing Ch. 12, Pg. 514-526

Parallelism in a Uniprocessor System

• A reconfigurable arithmetic pipeline is an example of parallelism in a uniprocessor system.
• Each stage of a reconfigurable arithmetic pipeline has a multiplexer at its input. The multiplexer may pass input data, or the data output from other stages, to the stage inputs. The control unit of the CPU sets the select signals of the multiplexer to control the flow of data, thus configuring the pipeline.

A Reconfigurable Pipeline With Data Flow for the Computation A[i]  B[i] * C[i] + D[i]

• 0
• 1
• MUX
• 2
• 3
• S1 S0

• 0
• 1
• MUX
• 2
• 3
• S1 S0

• 0
• 1
• MUX
• 2
• 3
• S1 S0

• 0
• 1
• MUX
• 2
• 3
• S1 S0

• *
• LATCH

• +
• LATCH

• |
• LATCH

• To
• memory
• and
• registers

• Data Inputs

• 0 0

• x x

• 0 1

• 1 1

• Although arithmetic pipelines can perform many iterations of the same operation in parallel, they cannot perform different operations simultaneously. To perform different arithmetic operations in parallel, a CPU may include a vectored arithmetic unit.

Vector Arithmetic Unit

• A vector arithmetic unit contains multiple functional units that perform addition, subtraction, and other functions. The control unit routes input values to the different functional units to allow the CPU to execute multiple instructions simultaneously.
• For the operations AB+C and DE-F, the CPU would route B and C to an adder and then route E and F to a subtractor for simultaneous execution.