The pic16F84 Microcontroller Part 3 Timer

The PIC16F84 has a block of 64 bytes of data that does not require power to retain its contents. This non-volatile memory is not part of the (volatile) Data store and is accessed through SPRs as a peripheral device. Any byte can be addressed and then read from or written to via the EEDATA register as addressed by the EEADR register and controlled by the EECON1 and EECON2 control file registers. Data EEPROM has a minimum endurance of 1,000,000 writes and such data is retained for upwards of 40 years.
Details of the Read and Write protocols are given in topic 15, but are briefly reviewed here for completeness.

Read

1. Put address (00 – 3Fh) into EEADR.
2. Set RD (bit0 of EECON1) to 1 to set to the ReaD mode.
3. Read the addressed contents in EEDATA. Write
1. Put address into EEADR.
2. Put data into EEDATA.
3. Set WREN (bit 2 of EECON1) to 1 to WRite ENable.
4. Put code 55h into EECON2.
5. Put code AAh into EECON2.
6. Begin the Write cycle by setting WR (bit 1 of EECON1) to 1.
Writing, which is normally an infrequent act, is deliberately made circuitous to protect against accidental changes to the EEPROM. The register EECON2 does not actually exist, but the interlock writing 5 5h followed directly by AAh to File 89h is a necessary part of unlocking the target byte. Interrupts can disrupt this sequence and should be inhibited if used. Writing takes around 50 ms to complete, and sets the EEIF (EEPROM Interrupt Flag) bit 4 of EECON1 after this time, and this can be used to interrupt the processor. The WRERR (WRite ERRor) bit 3 of EECON1 is set if a Write cycle is prematurely terminated, say, by an External reset. Registers associated with the Data EEPROM are:

EEDATA, File08h

This contains the addressed data after a Read action and holds data to be written into the addressed byte during a Write action.

EEADR, File09h

The 6-bit address of the target byte is placed here before a Read or Write cycle.

EECON1, File 88h