The top-down approach limits the dimensions of devices to what is technically achievable using

22
. 
(© American Chemical Society 2002.) (a) - (d) show the formation of a periodic superlattice of Si and SiGe
24
. (© American Chemical Society 2002.) (e) - (j) show results from the
formation of segments of GaAs and GaP, including analysis of the profiles at the interfaces and the luminescence from segments of GaAs inside GaP
25
. (© Nature 2002.)

---

REVIEW
FEATURE
a band offset in the conduction band of ~0.6 eV, given by
{
E
CB 
(InP) - 
E
CB
(InAs)}, not far from predictions based on
known bulk data. 
It is easy to see that just by varying the thickness of the
barrier, the tunnel resistance can be varied over an extremely
large range. This is illustrated in Fig. 10, where parts (a) and
(b) show the highly perfect and almost digital nature of the
controlled barrier thickness, while part (c) shows the effective
variation of the impedance over many orders of magnitude
with the single barrier thickness
27
. 
Before giving examples of 1D heterostructure devices that
can, and have been, realized in nanowires containing multiple
InAs/InP heterostructures, I will return to the ‘classical’
challenge of realizing DBRT devices in 1D-0D-1D, which has
been the target of top-down efforts for more than 15 years.
In Fig. 11, a structure is shown that was designed and grown
with InAs as the emitter and collector, and two 5 nm thick
tunnel barriers of InP on either side of the central InAs QD in
the form of a cylinder. The expected electronic structure of
the system is also shown, revealing the one-dimensional
density of states in the emitter from which electrons may
tunnel into the fully quantized electronic structure in the QD.
A peak in the 
I-V characteristics is expected with this
structure at an applied bias of 50-100 meV, in agreement
with the experimental curve, also shown in Fig. 11. These
device characteristics
27
are far superior to those reported for
conventional top-down 1D-0D-1D DBRT devices.
With the ability to make low-resistive ohmic contacts to
InAs nanowires, it should be possible to fabricate highly
perfect single-electron transistor (SET) devices using almost
the same technology as that for DBRT devices. It is merely
necessary to extend the central InAs segment to dimensions
such that quantum confinement is negligible and where the
Coulomb charging energy for the addition of another electron
to the central island dominates transport. A SET with InP
barriers ~5 nm thick and a 100 nm long island in between
has been successfully implemented, as summarized in Fig. 12.
For this type of SET, containing one Coulomb island
October 2003
2 9
Fig. 9 (a) and (b) show high-resolution transmission electron micrographs of InAs
containing InP barriers; (b) shows that the abruptness of these heterointerfaces is on the
scale of one or two monolayers. (c) is a band diagram of the potential landscape seen by
an electron in the InAs/InP nanowire, in which a thick segment of InP constitutes a
blocking barrier for electron transport along the InAs nanowire. The effect of this on
transport is shown in (d), where the linear and low resistive properties of a homogeneous
InAs nanowire is contrasted with the suppression of current in an InAs nanowire containing
a thick (80 nm) InP barrier. The band offset energies of the InAs/InP heterostructure
interfaces are deduced from measurements of the thermionic emission of electrons over
the barrier. From Arrhenius plots, such as shown in (e), the activation energy can be