Chapter 41 gmac ethernet Interface


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RK3288 TRM





Chapter 41 GMAC Ethernet Interface





    1. Overview

The GMAC Ethernet Controller provides a complete Ethernet interface from processor to a Reduced Media Independent Interface (RMII) and Reduced Gigabit Media Independent Interface (RGMII) compliant Ethernet PHY.
The GMAC includes a DMA controller. The DMA controller efficiently moves packet data from microprocessor’s RAM, formats the data for an IEEE 802.3-2002 compliant packet and transmits the data to an Ethernet Physical Interface (PHY). It also efficiently moves packet data from RXFIFO to microprocessor’s RAM.
      1. Features





  • Supports 10/100/1000-Mbps data transfer rates with the RGMII interfaces

  • Supports 10/100-Mbps data transfer rates with the RMII interfaces

  • Supports both full-duplex and half-duplex operation

    • Supports CSMA/CD Protocol for half-duplex operation

    • Supports packet bursting and frame extension in 1000 Mbps half-duplex operation

    • Supports IEEE 802.3x flow control for full-duplex operation

    • Optional forwarding of received pause control frames to the user application in full-duplex operation

    • Back-pressure support for half-duplex operation

    • Automatic transmission of zero-quanta pause frame on deassertion of flow control input in full-duplex operation

  • Preamble and start-of-frame data (SFD) insertion in Transmit, and deletion in Receive paths

  • Automatic CRC and pad generation controllable on a per-frame basis

  • Options for Automatic Pad/CRC Stripping on receive frames

  • Programmable frame length to support Standard Ethernet frames

  • Programmable InterFrameGap (40-96 bit times in steps of 8)

  • Supports a variety of flexible address filtering modes:

    • 64-bit Hash filter (optional) for multicast and uni-cast (DA) addresses

    • Option to pass all multicast addressed frames

    • Promiscuous mode support to pass all frames without any filtering for network monitoring

    • Passes all incoming packets (as per filter) with a status report

  • Separate 32-bit status returned for transmission and reception packets

  • Supports IEEE 802.1Q VLAN tag detection for reception frames

  • MDIO Master interface or PHY device configuration and management

  • Support detection of LAN w frames and AMD Magic Packet frames

  • Support checksum off-load for received IPv4 and TCP packets encapsulated by the Ethernet frame

  • Support checking IPv4 header checksum and TCP, UDP, or ICMP checksum encapsulated in IPv4 or IPv6 datagrams

  • Comprehensive status reporting for normal operation and transfers with errors

  • Support per-frame Transmit/Receive complete interrupt control

  • Supports 4-KB receive FIFO depths on reception.

  • Supports 2-KB FIFO depth on transmission

  • Automatic generation of PAUSE frame control or backpressure signal to the GMAC core based on Receive FIFO-fill (threshold configurable) level

  • Handles automatic retransmission of Collision frames for transmission

  • Discards frames on late collision, excessive collisions, excessive deferral and underrun conditions

  • AXI interface to any CPU or memory

  • Software can select the type of AXI burst (fixed and variable length burst) in the AXI Master interface

  • Supports internal loopback on the RGMII/RMII for debugging

  • Debug status register that gives status of FSMs in Transmit and Receive data-paths and FIFO fill-levels.




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