Design and realisation of integrated circuit tester
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INTEGRATED CIRCUIT TESTER pdf
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FAULTS AND TESTING METHODS Digital circuits deal with discrete signals known as digits. In digital circuit, discrete signals in the form of either pulse or voltage levels are manipulated as a discrete quantity. These discrete quantities are the representation of logic high or low. In digital test, we are dealing with either logic high or logic low at the input and expecting similar responses at the output of such circuit. Why testing the IC? Testing is a critical part of the manufacturing process included for a digital circuit device. The purpose of testing is for measurement of defects and quality level and Each integrated circuit that leaves the factory must be thoroughly checked in order to verify it will function as designed. Therefore, both the development of fault testing strategies and testing algorithm must be done as efficiently as possible so that it will provide a high probability of detecting any faulty circuit. A fault can be defined as any condition that causes a device to function improperly. The two primary objectives of testing are fault detection and fault location. Fault detection testing is the process of determining whether a fault is present in the tested circuit. Fault Detection Test Set (FDTS) is a set of inputs to a logic circuit that can be used to detect faults. FDTS is used to test a circuit to make sure it is fault free. Another one is Fault Location Test Set (FLTS) is a set of inputs that can be used to locate a fault. Fault coverage is defined as the percentage of all potential faults that are detected or located by the test. This configuration test set model is shows in Figure 1.6 Normally applying test vectors of a FDTS or FLTS to its inputs stimulates the circuit under test. Then capturing the responses to the test vectors from the outputs and comparing them to the expected results evaluate the function of the circuit. If the results are as expected, then the circuit is determined as a fault free circuit. In the automatic testing equipment (ATE), test vectors are stored in a memory from which they are retrieved and applied to the circuit under test by a microcontroller [2]. This operation is depicted clearly as in Figure Figure 1. 5: Example setup of an Automatic Test Equipment (ATE) For Built-In Self-Test (BITS), special circuit generates test patterns automatically. In an automatic testing equipment, expected value of results are retrieved from the memory as each test vector is applied on the circuit's inputs and comparing the results to the corresponding circuit output [2]. The model for Built-In Self-Test is depicts in Figure 3.2. Automatic Pattern Generator Circuit under Test Response Capture Figure 1. 6: Example setup of Built in Self-Test (BIST) A fault, defined as any condition that can cause the circuit to function improperly can be verified using test vectors or pattern. They can be used to detect the faulty circuit and by then they will be called Fault Detection Test Set (FDTS) or locate and they will be called Fault Location Test Set (FLTS). In any case, we apply the test vectors to the input, collect to the output and compare it with the expected results and decide. So, this logic is applied to ATE and all testers that use the BIST. So, our tester will follows those characteristics. In the section below, we will study different type of faults. Classification of faults Parametric and functional failures Those failures can affect only the parametric behavior of the circuit. In other words, the circuit realizes its function but with performances less than those expected. The detection of such failures can be tedious and requires specific tests. The other type of defect causes a catastrophic failure. This failure can range from the malfunctioning for a particular configuration of data {which might be complex in detecting) to a serious crash independent of data and which is easily detected [20]. The parametric failure or non-logical failure consists of the defect of some parameters of the ICs (current, voltage, time, temperature). On the other hand, the functional failure of the digital IC deals with logic state at each stages of the circuit. In this section, we will try to enumerate the different types of fault that can occur in digital logic circuit. There are many possible causes of fault in a digital circuit. Faults in the digital ICs are generally classified into two groups: static and dynamic faults. Static faults Static faults are characterized by an erroneous output that is constant for a given input condition, for the duration of a circuit state. The faulty condition does not change with time. The faulty output is maintained as long as the corresponding input held constant. It's also known as a permanent fault. Like a permanent open or short circuit Dynamic faults Dynamic faults are characterized by an erroneous output that exists for a very short period of time. These transient errors can be difficult to detect, requiring the use-of high-speed storage equipment. These faults appear and disappear with time. It's also known as intermittent fault, for instance, the sudden variation of the output current and voltage. Probable Faults Condition The most difficult aspect of fault analysis is discovering exactly where the fault had occurred. Fault may not be determined at the first glance as a single fault can causes other malfunctions. Static faults are most commonly found in IC package. Types of static faults are discussed next. Bridge faults Most digital circuits are assembled on fiberglass cards containing printed circuit on wire-wrap connections. Such cards usually support a multitude of interconnected IC packages. Adjacent terminals or printed circuit leads can become accidentally shorted together. This is known as bridge faults. This will affect the logic values of the shorted lines. If the two lines have different logic value, a conflict will be there. The resulting logic value may differ depending on the type of electronic logic that is being used. In the case of TTL devices, a bridge between two opposing signals results in a valid logic '0' voltage. Figure 3.3 shows a bridge fault at the output of two AND gate inside the 7408 IC package. For TTL devices, the value on the bridge line will be only '1' if both of the outputs are '1 Figure 1. 7: Bridge Fault within a 7408 AND gate package Broken or missing conductor Manufacturing defects of wiring errors can result in an open circuit where there should be a solid connection between two points. Thus, signals driven onto this line at the source never reach their destination. This fault resembles the stuck input and output faults, where the input or output remains constant. Figure below shows a missing connection inside a 7408 AND IC package Figure 1. 8: Example of missing conductor Types of test This section will emphasize on some types and method of test. Types of test are directly link to the types of fault. It is for this reason that for the parametric fault one has the parametric test and functional test for the functional failure. Parametric Test The parametric test or test of characterization on many circuits' sets, and prototypes for determining the circuit operating limits is performed at each new design or new manufacturing process under different conditions. Functioning Test Exhaustive Method Exhaustive method is a test method where all possible combination inputs are applied on the inputs of the circuit under test. For example to test a dual inputs AND logic, the test set will be (00, 01, 10, 11). The responses will be captured from the output of the circuit and compared with the table of results according to each input applied on the input of the circuit. This test method is-easy to generate and is a straightforward procedure. It provides 100% fault coverage and it is efficient to test a small and simple digital integrated circuit. But it will be impractical to test complex combination logic circuit and digital integrated circuit with High Fanin. If exhaustive method is implemented on a 30 inputs digital integrated circuit, it will take up to 30 minutes to test all input patterns in order to make sure the circuit is fault free. Besides that, exhaustive test may not be complete enough for sequential circuit where test vector order matters Random Method The random method is easy to use and can be applied with a low cost tester, to any type of circuit. Also, it enables to save necessary calculations to elaborate an input sequence as well as requires less storage place to stock it. The use of random test method presents the inconvenience of not giving any probabilistic nor deterministic indication on the state of the circuit under test (at least in the case where they obtained responses are similar to the reference's response). Test pattern generation A test pattern is a couple made up of a set of imposed input values and a set of expected output values. The test pattern generation consists of defining a program which will enable to describe the specific test's vectors for detecting the set of given faults in an aim of having optimum quality test and a test's application cost. The test pattern generation of a digital system consists of determining the stimuli to apply at the input of a circuit to underline a potential breakdown . The test pattern generation can be performed at different levels of the modeling at the level of the circuit description as well as the faults taken into account. There are many techniques to achieve this aim. Manual test pattern generation The test vectors are written manually by the test's engineer. It uses a faults' simulation and do not require an algorithm of generation. However, it is very difficult to reach a higher coverage rate this way. Pseudo random test pattern generation In this case, test vectors are choose randomly, by using a faults' simulation for determining the coverage rate, but does not detect difficult faults, this makes this generation techniques not to have an important industrial interest. Exhaustive test pattern generation This type of generation applies all possible test vectors without having to use faults' simulation (no faults' model). It detects all faults detectable of all faults models. However with a high number of vectors, it is very costly and unusable for circuits with a great number of inputs Automatic test pattern generation (ATPG) The ATPG uses a fault' simulation and deterministic test vector, for each fault none detected, a test vector which detect it is generated. It enables to reach a maximum coverage rate at a minimum cost. Conclusion At this level, we can say without any ambiguities that, it necessary to test regularly a digital IC to exhibit possible fault. Those faults can be test using two main methods: the HIST and ATE; both of this method have the same principle which consist to send a test vector at each input of the each logic IC and collect the output to be analyzed by comparing it to the normal functional digital IC: it also called functional test or exhaustive test. Fault can be classified in two main categories: Static and dynamic fault. It also has several models and probable faults that can occur. In the next chapter, we will study our tester based on exhaustive test since we will test only the SSI. The generation of the test vector will be done manually. CHAPTER TWO: METHODOLOGY AND MATERIAL This chapter will comprise of a detailed study of the system and how it functions, the study and dimensioning of each sub-block in the block diagram. Followed by the Electronic diagram of the system and the flowcharts used to develop the program. GENERAL BLOCK DIAGRAM Figure 2. 1: General Block Diagram OPERATION OF THE SYSTEM From the block diagram above, we see that we have five basic sub blocks, which consist of the Power Supply, the Control Unit, Display Unit, IC Sockets and the Keypad. The power supply produces three level of voltages; +5V,±12V. The +5V is used to supply the LCD, UC, and the IC sockets (all logic ICs and the NE555), while the ±12V is used the supply the IC socket which will hold the OPAM ICs. The control unit comprises of the microcontroller and the oscillating circuit. The microcontroller (PIC18F4520) contains the program which controls the functioning of the circuit the oscillating circuit made of quartz and two ceramic capacitors produces a precisely defined and stable frequency and generates the pulses to the microcontroller . It sends and receives signals from the ICs to be tested, and displays the result on the LCD The display unit contains the 4X20 LCD, permits us to visualize the functioning of the system. The keypad enables the different ICs to be selected and tested. The IC sockets are 4 in number, and the hold the ICs to be tested. Now we shall proceed with the dimensioning of each block. 2.2.1. Power Supply Figure 2. 2: Block diagram of a regulated power supply This is a circuit that converts high AC signals into low regulated DC signals. It supplies stable voltage to a circuit that must be operated within certain supply limits. In our study, we will use two output voltage levels. +5V to supply PIC microcontroller, logic ICs, LCD display, NE555. And the ±12V to supply LM741. A backup power supply can also be created using the same circuit diagram but the input to the circuit will be supplied by a 9V battery. The only disadvantage is that, the circuit may only be able to produce 5V which will be used to supply the main board and NE555. Specifications Transformer The microcontroller needs a maximum of 300mA, the LCD needs a maximum of 10mA, passive components can need a max of 150mA, for the ICs to be tested, we reserve 40mA, and hence we have a total of 500mA. The microcontroller, LCD, and NE555 circuit take 5v while the OPAM IC takes ±12V. The transformer is to step down the input A.C voltage. In this case, we used a center tapped transformer 220V-AC/12*12V/1A/50Hz/s=24VA. Rectifier The rectifier converts the A.C signals into D.C voltage. The rectifier makes use of diodes in the conversion process. It may be half wave or full wave rectifier. In our project, we used a basic integrated circuit bridge rectifier package for the rectification purpose. This package has the following specifications: Single phase low cost bridge rectifier Maximum input voltage of 280V (Vrms) Maximum Average forward current 4A Maximum DC blocking voltage 400V Maximum instantaneous forward drop per diode 1.1V at IF = 4 A The output voltage is given by 42 X Vrms — 1.4 = 42 X 24 — 1.4 = 32.54V Therefore the output from the bridge package in our system is 15X42 — 1.4 = 19.81V Hence from the datasheet, we choose KBL04 bridge rectifier. The output of this rectifier is D.C in the sense that its current is in one direction. The voltage is still varying in a large amount. The voltage still swings between 0V and the peak. Further processing must be done on the voltage to minimize the voltage swing. Filtering and smoothening The voltage coming from the rectification unit still contains some A.C components. In order to remove these A.C components, we need to pass it through a filtering capacitor. A ceramic capacitor will stabilize the IC regulators preventing it from oscillating- smoothening. Hence we have: C1 = C2 0.5 2X13.54X50 369.27^F Download 0.86 Mb. Do'stlaringiz bilan baham: 
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